MP3 decoding on FPGA: a case study for floating point acceleration
نویسندگان
چکیده
Reconfigurable devices are becoming an extremely attractive means for computing and prototyping. The main reasons for their popularity are fast turnaround time, cheap implementation (low/medium volume), easier design flow (no physical implementation or fabrication involvement), and great speed-up potential through application parallelism mapping on the reconfigurable fabric. Moreover, with embedded hard core and soft core processors, reconfigurable devices provide an excellent framework for hardware-software co-design with even shorter total turnaround time. This work constitutes a case study for the acceleration of Floating Point (FP) applications, using the NIOS2 processor. Our case study is based on a software MP3 decoder implementation that heavily relies on floating point math. NIOS2 is a simple microprocessor that has no integrated floating point (FP) units; thus, a set of FP accelerators is necessary for achieving real-time or faster decoding. We explore two main issues: i) the speedup and efficiency of FP accelerators on the FPGA; and ii) the effect of communication overhead between the processor and the FP accelerators. We show that real-time decoding is possible by leveraging a) simple software modifications, b) efficient accelerator designs, and c) smart parallelism extraction strategies.
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